Resonant clock distribution networks have recently been proposed for the energy-efficient distribution of clock signals in synchronous digital systems. In these networks, energy-efficient operation is achieved using one or more inductors to resonate the parasitic capacitance of the clock distribution network. Clock distribution with extremely low jitter is achieved through reduction in the number of clock buffers. Moreover, extremely low skew is achieved among the distributed clock signals through the design of relatively symmetric all-metal distribution networks. Overall network performance depends on operating speed and total network inductance, resistance, size, and topology, with lower-resistance symmetric networks resulting in lower jitter, skew, and energy consumption when designed with adequate inductance.
In resonant clock distribution networks, the amount of energy injected into the clock network depends on certain design parameters, including the size of the final clock drivers, and the duty cycle of the reference clock signals that drive the final clock drivers. Furthermore, in contrast to conventional (that is, non-resonant) clock distribution networks, the amount of energy injected into the resonant network also depends on the frequency at which the network is operated. In general, larger driver sizes or longer duty cycles allow for more current to build up in the inductive elements, thus ultimately injecting more energy into the clock network, and resulting in faster clock rise times or larger clock amplitudes. Moreover, for fixed driver size and duty cycle, operation at a low frequency results in faster clock rise times and larger clock amplitudes than operation at a relatively higher frequency, since the final clock drivers conduct for a longer time, thus again allowing for more current to build up in the inductive elements and the injecting of more energy into the clock network.
Testing presents a challenge related with the use of resonant clock distribution networks in digital devices. Specifically, in a particular mode of testing called single-stepping, a specific bit pattern is first loaded onto specified scan registers (scan-in mode). The digital system is then operated for one clock cycle. To validate correct function, the contents of the scan registers are then read (scan-out mode). Resonant clock distribution networks typically require multiple clock cycles of operation before they are able to provide their specified clock amplitude. Moreover, they require multiple clock cycles until their clock waveforms stop oscillating. Therefore, switching from scan-in mode to a single cycle of operation is a challenge.
It is possible to address the above challenges in ways that are likely to be impractical for many designs. For example, it is possible to design resonant clock drivers so that they are capable of operating in conventional mode. These derivers typically rely on a switch that is introduced in series to the clock load, thus increasing overall resistance of the resonant clock network and degrading its energy efficiency when operating in resonant mode.
Another approach of limited practicality is to use a high-speed global enable signal to disable the clocked registers for as long as it takes for the resonant clock waveform to reach its full amplitude, and at the end of the single test clock cycle that follows the scan-in of data. Such a signal must enable all clocked registers on the same cycle after the resonant clock signal has reached full amplitude. However, the design of a network that distributes such a high-speed enable signal with acceptable skew and correct relative timing with respect to the clock requires significant additional engineering effort and physical resources (for example, signal drivers and routing tracks).
Architectures for resonant clock distribution networks have been described and empirically evaluated in the following articles: “A 225 MHz Resonant Clocked ASIC Chip,” by Ziesler C., et al., International Symposium on Low-Power Electronic Design, August 2003; “Energy Recovery Clocking Scheme and Flip-Flops for Ultra Low-Energy Applications,” by Cooke, M., et al., International Symposium on Low-Power Electronic Design, August 2003; and “Resonant Clocking Using Distributed Parasitic Capacitance,” by Drake, A., et al., Journal of Solid-State Circuits, Vol. 39, No. 9, September 2004; “A 1.1 GHz Charge Recovery Logic,” by Sathe V., et al., International Solid-State Circuits Conference, February 2006; “900 MHz to 1.2 GHz two-phase resonant clock network with programmable driver and loading,” by Chueh J.-Y., et al., IEEE 2006 Custom Integrated Circuits Conference, September 2006; “A 0.8-1.2 GHz frequency tunable single-phase resonant-clocked FIR filter,” by Sathe V., et al., IEEE 2007 Custom Integrated Circuits Conference, September 2007. In all these articles, resonant clock distribution networks are investigated in the context of energy efficiency. These articles do not describe any approaches to testing or, in particular, single-stepping in resonant clock networks.
A resonant clock driver that is also capable of operating in conventional mode has been described in the article “A Resonant Global Clock Distribution for the Cell Broadband Engine Processor,” by Chan S., et al., IEEE Journal of Solid State Circuits, Vol. 44, No. 1, January 2009. The resonant clock driver in this article includes a switch in series to the clock load, thus resulting in relatively lower energy efficiency when the resonant clock network is operating in resonant mode.
Overall, the examples herein of some prior or related systems and their associated limitations are intended to be illustrative and not exclusive. Other limitations of existing or prior systems will become apparent to those of skill in the art upon reading the following Detailed Description.